In microstructures such as integrated circuits, a large number of elements, such as transistors, capacitors and resistors, are fabricated on a single semiconductor wafer by depositing semiconductive, conductive and insulating material layers and patterning these layers by photolithography and etch techniques. Frequently, the problem arises that the patterning of a subsequent material layer is adversely affected by a pronounced topography of the previously formed material layers. Moreover, the fabrication of microstructures often requires the removal of excess material of a previously deposited material layer. The repeated patterning of material layers, however, creates an increasingly non-planar surface topography, which may deteriorate subsequent patterning processes, especially for microstructures that include features with minimum dimensions in the submicron range, as is the case for sophisticated integrated circuits. Planar surface topography is desirable for various reasons. For example, photolithography has a limited optical depth of focus and non-planar surface topography may impact precision of pattern formation through photolithography. Additionally, electrical insulation between adjacent structures may be compromised if planar topography is not maintained.
Chemical mechanical planarization (CMP) is a common technique employed during fabrication of the integrated circuits to remove excess materials and to achieve planar layers for subsequent material deposition. CMP generally involves polishing an exposed surface of a wafer or layer formed thereon using a polishing pad that is disposed on a rotatable platen. As industry moves to manufacture nodes on an ever-decreasing size scale, CMP specifications continue to tighten and defects in a polishing surface of the polishing pad may contribute to inconsistent planarization between different wafers and/or in different regions within individual wafers. Defects in the polishing surface may arise during manufacture of the polishing pad and/or during CMP, and examples of defects include bubbles or uneven wear of the polishing surface.
Existing quality control techniques include pretreatment of the polishing pads by a third party supplier, which generally involves shipping the polishing pads to the third party supplier for pre-shaping and/or pre-surfacing. The polishing pads are then shipped to a fabrication facility and mounted on the rotatable platen. However, such pre-treatment is costly, time consuming, inconvenient, and does not address quality issues that arise after usage of the polishing pads commences. To address quality issues during usage of the polishing pads, processed wafers must be examined after CMP to measure the surface topography. However, such techniques often result in significant delay in identifying CMP problems, are time consuming, and result in significant product waste.
Accordingly, it is desirable to provide wafer processing apparatuses that are employed to perform CMP and methods of operating the wafer processing apparatuses that enable earlier identification of CMP problems as compared to examination of processed wafers. Additionally, it is desirable to provide wafer processing apparatuses and methods of operating the wafer processing apparatuses that enable product waste to be minimized. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.